HyperRAM Memory Model

Overview

HyperRAM Memory Model provides an smart way to verify the HyperRAM component of a SOC or a ASIC. The SmartDV's HyperRAM memory model is fully compliant with standard HyperRAM Specification and provides the following features. Better than Denali Memory Models.

HyperRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

HyperRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports HyperRAM memory devices from all leading vendors.
Supports 100% Cypress HyperRAM specification standard.
Supports all the HyperRAM commands as per the specs.
Supports 64 Mb,128 Mb Memory Density
Supports 8-bit data bus (DQ[7:0])
Supports Read-Write Data Strobe (RWDS)
Supports Device Identification Registers.
Supports Configuration Registers.
Supports Double-Data Rate (DDR) - two data transfers per clock.
Supports Sequential burst transactions.
Supports for Hardware reset.
Supports following Configurable burst characteristics.

Wrapped burst length options
128 Bytes (64 clocks)
64 Bytes (32 clocks)
32 Bytes (16 clocks)
16 Bytes (8 clocks)
Linear burst
Hybrid option - one wrapped burst followed by linear burst
Wrapped or linear burst type selected in each transaction

Supports Low Power Modes
Supports Configurable output drive strength.
Checks for following

Check-points include power up, initialization and power off rules
State based rules
All timing violations

Supports following Power Conservation Modes.

Interface Standby
Active Clock Stop
Deep Power-Down

Supports all types of timing and protocol violation detection.
Constantly monitors HyperRAM behavior during simulation.
Protocol checker fully compliant with Cypress HyperRAM Specification.
Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of HyperRAM designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the HyperRAM testcases.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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