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GDDR3L Memory Model

Overview

GDDR3L Memory Model provides an smart way to verify the GDDR3L component of a SOC or a ASIC. The SmartDV's GDDR3L memory model is fully compliant with standard GDDR3L Specification and provides the following features. Better than Denali Memory Models.

GDDR3L Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

GDDR3L Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports GDDR3L memory devices from all leading vendors.
  • Supports 100% of GDDR3L protocol standard.
  • Supports all the GDDR3L commands as per the specs.
  • Quickly validates the implementation of the GDDR3L standard GDDR3L Specification.
  • Supports for programmable clock frequency of operation.
  • Supports for all types of timing and protocol violation detection.
  • Supports for All Mode register programming.
  • Supports for 8 bank operation.
  • Supports for Nominal and dynamic on-die termination (ODT) for data strobe and mask signals.
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
  • Supports for Bidirectional differential data strobe.
  • Supports for Programmable Burst length: 4, 8.
  • Supports for Programmable sequential/interleave burst mode.
  • Supports for Programmable CAS Read latency.
  • Supports for Programmable CAS Write latency.
  • Supports for Selectable BC4 or BL8 on-the-fly (OTF).
  • Supports for Self refresh mode.
  • Supports for Automatic self-refresh (ASR).
  • Supports for Write leveling.
  • Supports for Multipurpose register.
  • Supports for Write data mask function.
  • Supports for Output driver calibration.
  • Supports for On-die termination (ODT).
  • Supports for input clock stop and frequency change.
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Protocol checker fully compliant with GDDR3L Specification.
  • Constantly monitors GDDR3L behavior during simulation.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of GDDR3L designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

GDDR3L Memory Model Block Diagram

Deliverables

  • Complete regression suite containing all the GDDR3L testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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