FPMRAM Memory Model provides an smart way to verify the FPMRAM component of a SOC or a ASIC. The SmartDV's FPMRAM memory model is fully compliant with standard FPMRAM Specification and provides the following features. Better than Denali Memory Models.
FPMRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
FPMRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.