FCRAM Memory Model

Overview

Key Features

• Supports FCRAM memory devices from all leading vendors.
• Supports 100% of FCRAM protocol standard FCRAM specifications.
• Supports all the FCRAM commands as per the specs.
• Supports up to 512MB device density.
• Supports up to four internal banks.
• Supports Programmable Write latency.
• Supports the following burst lengths.
• 2
• 4
• 8
• 16
• Supports sequential burst type.
• Supports burst order.
• Supports all mode registers programming.
• Checks for following
• Check-points include power on, Initialization and power off rules,
• State based rules, Active Command rules,
• Read/Write Command rules etc.
• All timing violations.
• Supports for Self Refresh, Power down and deep power down operation.
• Supports for Auto refresh operation.
• Supports Additional RDQS Toggle (ART).
• Supports write data mask and data strobe features.
• Supports Background refresh and burst terminate operations.
• Supports Clock Stop Capability during idle periods.
• Supports all types of timing and protocol violation detection.
• Constantly monitors FCRAM behavior during simulation.
• Protocol Checker fully compliant with FCRAM Specification.
• Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Built in functional coverage analysis.
• Supports Callbacks, so that user can access the data observed by monitor.

Benefits

• Faster testbench development and more complete verification of FCRAM designs.
• Easy to use command interface simplifies monitor control and configuration.
• Simplifies results analysis.
• Runs in every major simulation environment.

Block Diagram

Deliverables

• Complete regression suite containing all the FCRAM testcases.
• Examples showing how to connect and usage of Model.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

Technical Specifications