IP Catalog > Memory & Libraries IP > Embedded Memories IP > RAM IP > Other > FRAM Memory Model

FRAM Memory Model

Overview

FRAM Memory Model provides an smart way to verify the FRAM component of a SOC or a ASIC. The SmartDV's FRAM memory model is fully compliant with standard FRAM Specification and provides the following features. Better than Denali Memory Models.

FRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

FRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports FRAM memory devices from all leading vendors.
  • Supports 100% of FRAM protocol standard FM25V10, FM22L16, FM28V202A, DS501-00051-1v0-E, and DS411-00005-3v0-E.
  • Supports all the FRAM commands as per the specs.
  • Quickly validates the implementation of the FRAM standard FM25V10, FM22L16, FM28V202A, DS501-00051-1v0-E, and DS411-00005-3v0-E.
  • Supports programmable clock frequency of operation.
  • Supports for all types of timing and protocol violation detection.
  • Supports for 1-Mbit F-RAM logically organized as 128K × 8.
  • Supports for Very fast serial peripheral interface (SPI).
    • Up to 40-MHz frequency.
    • Direct hardware replacement for serial flash and EEPROM.
    • Supports SPI mode 0 (0, 0) and mode 3 (1, 1).
  • Supports for Sophisticated write protection scheme.
    • Hardware protection using the Write Protect (WP) pin.
    • Software protection using Write Disable instruction.
    • Software block protection for 1/4, 1/2, or entire array.
  • Supports for 2-Mbit F-RAM logically organized as 128K × 16.
  • Supports for 4-Mbit F-RAM logically organized as 256K × 16.
  • Supports for Software-programmable block write-protect.
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
  • Supports for input clock stop and frequency change.
  • Constantly monitors FRAM behavior during simulation.
  • Supports Protocol checker fully compliant with FRAM Specification FM25V10, FM22L16, FM28V202A, DS501-00051-1v0-E, and DS411-00005-3v0-E.
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of FRAM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

FRAM Memory Model Block Diagram

Deliverables

  • Complete regression suite containing all the FRAM testcases.
  • Complete UVM/OVM sequence library for FRAM controller.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info

Related IPs

×
Semiconductor IP