Hyper-Decoupling Capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancement and an Energy Harvesting capabilities

Overview

The CC-100 IP is a Hyper-decoupling capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancement and an Energy Harvesting capabilities. The Hyper-Bypass Capacitor IP creates the lowest Impedance point in IC power grids aiding in maximum on chip supply line filtering, showing an up to a 600X improvement in effective and reservoir capacitance. The IP features a circuit noise activated dynamic input current controlled reservoir capacitance, and can function as a “stand-alone” on Chip DCAP, or work in parallel with existing DCAP structures. Due to the embedded IP negative feedback, the CC-100 features a 25% reduction in capacitor effective series inductance (ESL). The IP operates by feeding back a portion (nominally 20%) of the bypass current flowing through the front end on chip input base capacitors, feeding back current onto the chip power grid, preventing bypass Capacitor Deep discharge, thus reducing overall chip dynamic power draw. These effects substantially reduce RF Emissions from chip power grids making systems less vulnerable to cyber hacking and more secure. The IP draws no current for operation, thus maximizing block efficiency.
The Super Cap IP is meant to replace or work in parallel with existing on chip decoupling capacitors, thus can be shaped into various aspect ratios and sizes to fit on-chip “white space”, the area under power grids, etc. in the same fashion as typical on-chip decoupling capacitors. In similar fashion to typical decoupling capacitors, the IP blocks can be connected in parallel to increase overall RF emission reduction, reservoir capability, and effective capacitance.

Key Features

Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
Up to a 36% Dynamic Power and RF Emissions Reduction
On-Chip Cybersecurity Enhancement
25% Reduction in Capacitor ESL
Provides the lowest impedance point in IC power-grids
Can work in parallel with existing IC DCAPs
Fits into any On chip footprint
Ability to port to any manufacturing process
Customizable design is not needed to support the operation of the device or IP.

Benefits

Enables Lowest Possible Dynamic Power Dissipation and RF Emissions
Activates when the System/Chip is Active(Circuit noise activated)
Enables Lowest possible Supply Line Noise--increasing IC sensitivity
Creates the lowest Impedance point in IC Power-Grids
Suppresses Frequencies Hackers use to gain access to Computers and embedded systems
No software to load for block activation
Adjustable Aspect ratio--fits into any circuit area,
Draws No DC power for Operation

Block Diagram

Hyper-Decoupling Capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancement and an Energy Harvesting capabilities Block Diagram

Video

A DC and Spectral Demonstration of the CC-100 Power Reduction and Cyber Security Enhancement capabilities aka the PowerStic Module

A video demonstration of the CC_100IP embedded in USB devices

Applications

On chip DCAP replacement--At least a 600X increase in effective capacitiance
Power Supply Decoupling in ICs
RF Emissions reduction
Dynamic Power reduction
Power Reduction and Cyber Security Enhancements in Digital, Mixed Signal, and Processor chips

Deliverables

Working Silicon Loaner Samples
Behavioral Model
Datasheet
.gds view
LEF view
2 to 3 week custom spin time
Customizable Circuit Design
Design Support
Datasheet-cut and paste the URL into a web browser to view
Behavioral Model-cut and paste the URL into a web browser to view

Technical Specifications

Foundry, Node

Any--portable to any process node

Maturity

Mature in Production

Availability

February 1, 2018

GLOBALFOUNDRIES

In Production: 180nm , 180nm LL , 180nm LL , 180nm LP , 180nm LP
Pre-Silicon: 180nm LP
Silicon Proven: 180nm , 180nm LL , 180nm LL , 180nm LP , 180nm LP

Tower

Silicon Proven: 180nm

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