The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a complete set of features that enable users to define an optimized PCS in products across a range of 100G Ethernet applications.
The IP, available in single port or quad port configurations, is designed to be used with the 100G Ethernet MAC IP to deliver a complete system solution. The quad port 100G Ethernet PCS IP can be configured as a 2x100G PCS or a 4x50G/25G/10G PCS interfacing with a 4-lane 56G PHY. The single port IP can be configured as one of 4x25G, 2x50G or 1x100G interfacing with a PHY.
The 100G Ethernet PCS IP offers a comprehensive set of features including 100G scrambler/descrambler, 64b/66b encoder/decoder, multi-lane distribution, alignment marker insertion/striping, block synchronization and gearbox, and clock decoupling FIFOs. The multiplexed Reed-Solomon Forward Error Correction (RS-FEC) function provides different channels at various speeds. The IP implements a CGMII on the application side and four lanes interface to the PHY on the line side.
