High Speed Ethernet 100G MAC IP

Overview

The 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 specification. The IP provides a complete set of features that enable the user to define an optimized MAC in products across a range of 100G/200G/400G/800G applications.

The IP passes received MAC frames without modification to the user application or to the Ethernet line. In addition, the IP supports IEEE-managed objects, IETF MIB-II and RMON for management applications (e.g., SNMP). On the application side, the 100G/200G/400G/800G Ethernet MAC IP implements a flexible FIFO interface that can be connected to a user application. On the Ethernet line side, the IP implements a 1024-bit CDMII (800G Media Independent Interface) to connect to an 800G PCS. When operating in 200G/400G or 400G speeds, the IP implements a 512-bit CDMII to connect to a 200G/400G PCS. The 100G Ethernet MAC IP implements a wide CGMII/XLGMII (100G/40G Medium Independent Interface) that supports a 10G operation.

The 100G/200G/400G/800G Ethernet MAC IP seamlessly interoperates with the 00G/200G/400G/800G Ethernet PCS IP and the 112G Ethernet PHY IP to provide a complete Ethernet MAC, PCS and PHY solution for 100G/200G/400G/800G systems

Key Features

  • Supports all required features of the IEEE 802.3bs specification
  • Supports IEEE-managed objects, IETF MIB-II and RMON for management applications
  • Application interface includes the Synopsys native interface 512-bit or 1024-bit FIFO for more than 200G operation
  • Designed to be used with Synopsys 100G/200G/400G/800G Ethernet PCS IP
  • Supports IEEE 1588 applications
  • Silicon-proven

Block Diagram

High Speed Ethernet 100G MAC IP Block Diagram

Technical Specifications

×
Semiconductor IP