High performance dual-issue, out-of-order, 7-stage Vector processor (DSP) IP

Overview

World's first audio DSP IP with RISC-V Vector processor architecture
RiVAI-V1 is a dual-issue, Out-of-Order execution, 7-stage pipeline, 32-bit RISC-V processor core that supports the RV32IMFAC instruction set and customized Vector extension, as well as partial P extension. It is a real-time high-performance DSP IP, which can boost the performance of voice, audio, video, image and AI processing. Its “F” extensions support IEEE 754-compliant single precision floating point instructions, as well. The width of the Vector Register is 512 bits, including register renaming, and the memory access width is 256 bits. This greatly enhances memory bandwidth and reduces memory latencies for applications with intensive memory accesses. In addition, RiVAI-V1 features an advanced low-power, dynamic branch-prediction mechanism for efficient branch execution, instruction and data caches, local memories, and ECC error protection. It also includes a vectored and preemptive interrupt controller to serve diversified system events, an AHB bus, rich power management, and JTAG debug and trace interface for software development support.

Key Features

  • Dual-issue, out-of-order CPU architecture with a 7-stage pipeline.
  • 32-bit RISC-V ISA, supporting RV32IMFAC sets.
  • Supports customized Vector extension instruction set, and partial P extension.
  • Powerful general-purpose Digital Signal Processing (DSP) unit.
  • 256-bit Vector ALU and Load/Store architecture.
  • 512-bit Vector register length, which supports 32-bit x 16 MAC or 16-bit x 32 MAC operation.
  • Supports 16-bit, 32-bit fixed-point number operation, including integer and Q types.
  • Optional single-issue/multi-issue micro-architecture, partial sequential issue and OOO execution.
  • Equipped with instruction prefetch unit and dynamic branch prediction unit (BTB, BHT, RAS, JAL).
  • Supports Physical Memory Protection (PMP).
  • Supports Platform-Level Interrupt Controller (PLIC), 64 interrupts.
  • Supports fast interruption and fast access to achieve more efficient real-time operation.
  • Two privileges: Machine(M), User(U), and optional Supervisor(S) privilege.
  • External AHB bus, 256-bit, RiVAI-V1 core can be either master or slave.
  • Supports RISC-V debugging standard spec, supports JTAG.
  • Flexible parameterized configuration:
    • I-Cache/D-Cache space size
    • ITCM/DTCM space size
    • L2 SRAM size
    • The number of interrupts
    • Optional Floating-point unit (FPU)
    • Optional Vector processing unit (VPU)
    • Optional Memory management unit (MMU)

Benefits

  • Design Flexibility
    • The RISC-V ISA offers a compelling level of flexibility, and RiVAI has capitalized on this with our product portfolio. The RiVAI-V1 Vector processor is able to build fit-for-purpose products that align with customer requirements and application workloads, with its easy arrangement of preemptive interrupts, size of I-Cache/D-Cache or ITCM/DTCM and L2 SRAM, and other optional modules like FPU, MMU…, thus, taking us further into the higher performance DSP market space.
  • Portability
    • One of the most unique and powerful capabilities of the RISC-V Vector Extension is that the ISA is vector-length agnostic. This means that code written for a RiVAI-V1 vector processor can run on any compatible RISC-V vector ISA processor, so it’s possible to experiment with different vector sizes to achieve the perfect balance of performance, power, and area for different application workloads, and projects are easily portable between processors and applications.
  • Ease of programmability
    • The RiVAI-V1 DSP vector processor’s new solution integrates a superscalar unit and a Vector unit in a single SOC, using the same set of software development tools, which makes it very easy to write code; This solution replaces the chaotic situation of incompatibility between multi-IP vendors and multiple development platforms.
  • Use of standard software
    • RVV is an open standard, and much of the code written for RVV will be available in the open source domain. This allows developers to access the large and growing ecosystem of RVV-based algorithms, along with access to a full range of open source and commercial grade tools for compilation, modeling, debug, and trace. These standard and stable algorithms developing methods can greatly reduce development costs, allowing developers to quickly move to the market.
  • Power and performance efficiency
    • The flexibility and scalability of the RISC-V architecture makes it easy for RiVAI-V1 to build fit-for-purpose products for customers. The optimal system design, which is based on domain specific application (DSA), achieves the right balance of performance for the application workload within a defined power constraint. By selecting single-core, multi-core, or multi-clustered systems, the RiVAI Vector solution provides different vector/scalar/multi-core combined processor IPs on demand, helping customers achieve maximum performance efficiency while balancing their minimum area and power requirements.

Block Diagram

High performance dual-issue, out-of-order, 7-stage Vector processor (DSP) IP Block Diagram

Applications

  • Audio/Video DSP and Image Processing.
  • Networking and Communications, industrial control.
  • Advanced Driver-Assistance Systems.
  • Smart wireless switch/router; data center, storage.
  • Artificial Intelligence (Ai), Machine/Deep Learning, Neural Network, Speech recognition…

Deliverables

  • RTL Evaluation
  • Test Bench RTL
  • Software Development Kit
  • FPGA Bitstream
  • Documentation

Technical Specifications

Foundry, Node
All
Maturity
golden,silicon_proven
Availability
now
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Semiconductor IP