HDMI Intel® FPGA IP Core

Overview

The HDMI Intel FPGA intellectual property (IP) core provides support for the next generation of video display interface technology. Due to its ability to send high-definition audio and video, High-Definition Multimedia Interface (HDMI) has become the most common digital connection in consumer electronics.

The HDMI cable and connectors carry four differential pairs that are composed of three Transition-minimized differential signaling (TMDS) data channels and one clock channel in HDMI 2.0 or four Fixed Rate Link (FRL) data channels in HDMI 2.1. You can use these channels to carry video, audio, and auxiliary data at a raw bit rate of up to 3.4/6/8/10/12 Gbps per channel. HDCP-encrypted transmission can also be integrated into our IP through the newly released Intel® FPGA HDCP core.

Features

IP Core Feature

Description

Color support

  • 8, 10, 12 or 16 bits per color (bpc)
  • RGB and YCbCr 444, 422 and 420 color modes

Symbols per clock

1, 2, 4 or 8 symbols per clock

Video

Support up to 8k

Audio

Up to 32 channels of embedded audio

Block Diagram

HDMI Intel® FPGA IP Core Block Diagram

Technical Specifications

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Semiconductor IP