The HDMI V2.1 Tx provides a complete single-link HDMI transmitter function complies with HDMI specification version 2.1. It consists of two modules, a physical layer and a link module. The PHY is upper compatible with DVI transmitter and implemented as a hard IP based on an TSMC 28nm HPC+ process, while the link module is implemented as a synthesizable soft IP. Built-in High-bandwidth Digital Content Protection (HDCP) cipher function protects the transmission of audio-visual contents.
The HDMI V2.1 Rx provides a complete single-link HDMI receiver function complies with HDMI specification version 2.1. It consists of two modules, a physical layer (PHY) and a link module. The PHY is upper compatible with DVI receiver and implemented as a hard IP based on an TSMC 28nm HPC+ process, while the link module is implemented as a synthesizable soft IP. Built-in High-bandwidth Digital Content Protection (HDCP) cipher function protects the transmission of audio-visual content.
HDMI 2.1 Tx- Rx PHY & Controller IP (Silicon Proven in TSMC 28HPC+)
Overview
Key Features
- HDMI version 2.1 compliant transmitter and sink function
- Supports Dynamic HDR, FRL, VRR and Fast V active
- Wide range channel speed up to 12Gbps
- HDCP revision 1.4/2.2 compliant content protection
- Programmable PLL characteristics, transmitter swing voltage, and pre-emphasis
- Programmable PLL characteristics, channel delay, and on-chip terminator.
- 0.9V/1.8V power supply - Tx
- 0.9V/1.8V/3.3V power supply – Rx
- HDMI1.4b/HDMI2.0b/HDMI2.1 Compliant (Support FRL/EMpacket), 3Lane(3Gbps/6Gbps)/4Lane(6Gbps/8Gbps)
- Band width: 250Mbps~12Gbps/ch
Block Diagram
Applications
- Digital TV
- Tablets
- Mobile phones
- Digital camera
- Camcorders
- Soundbars
- Audio/Video Receivers
- DVD players
- Recorders
- Streaming-media players
- Set-top boxes
- Home theater systems
- Game consoles
Deliverables
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
- Documentation
- Design Guide
- Verification Guide
- Synthesis Guide
Technical Specifications
Foundry, Node
TSMC 28HPC+
Maturity
In Production
Availability
Immediate
Related IPs
- DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
- HBM3 Solution enabling access to HBM3 Controller and HBM3 PHY in TSMC N5 1.2V
- HBM3 V2 Solution enabling access to HBM3 Controller and HBM3 PHY in TSMC N3E
- DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
- HDMI 2.1 Tx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
- HDMI 2.1 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+