HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in GF 65/55LPe

Overview

The HDMI receiver PHY (Physical layer), a single-port IP core, fully conforms with HDMI 1.4's requirements. This HDMI RX PHY supports TMDS rates between 25MHz and 225MHz and offers a simple system LSI solution for consumer electronics like HDTV. The HDMI receiver PHY and the HDMI receiver link IP core collaborate most effectively. The following Fab/Nodes have all undergone Silicon Proving: (GF, Samsung, TSMC, UMC, SMIC, STMicro) Link Controller for an HDMI receiver that abides by HDMI 1.4a specifications to the letter. For consumer electronics like HD-TVs and AV receivers, this offers a simple system-on-chip (SOC) implementation. When used in conjunction with our complementing HMDI receiver PHY IP core, it performs at its best. The core functions of HDMI can be modified to meet requirements.

Key Features

HDMI version 1.4 compliant receiver
Supports DTV from 480i to 1080i/p HD resolution
Supports 24bit, 30bit and 36bit color depth per pixel
HDMI version 1.4a, HDCP revision 1.3 and DVI version 1.0 compliant receiver
Supports DTV from 480i to 1080i/p HD resolution, and PC from VGA to UXGA
Supports 3D video format specified in HDMI 1.4a specification
Programmable 2-way color space converter
Compliant with EIA/CEA-861D
Deep color supported up to 16bit per pixel
xvYCC Enhanced Colorimetry
All packet reception including Gamut Metadata Packet
Supports RGB, YCbCr digital video output format including ITU.656
24/30/36/48bit RGB/YCbCr 4:4:4
16/20/24bit YCbCr 4:2:2
8/10/12bit YCbCr 4:2:2 (ITU.601 and 656)
48 bit mode is not supported in 1080p
Supports standard SPDIF output for stereo or compressed audio up to 192KHz
Support PCM, Dolby digital, DTS digital audio output through 4bits I2S up to 8 channel
IEC60958 or IEC61937 compatible
1bit audio format (Super Audio CD) output
High-bitrate compressed audio formats output
Slave I2C interface for DDC connection
Configuration registers programmable via synchronized parallel interface
Interface to external HDCP key storage
Integrated cable terminator
Adaptive equalizer for cable
Adjustable analog characteristics
PLL band width
VCO gain, BGR voltage
Cable terminator resistance value
DLL digital filter characteristics
Integrated Audio PLL
3.3V/2.5V/1.0V power supply
Silicon Proven in GF 65/55LPe.

Block Diagram

Deliverables

Datasheet and Integration guideline
GDSII or Phantom GDSII
Layer map table
CDL netlist for LVS
Verilog behavior model
Liberty timing model
DRC/LVS/ERC results
Configurable RTL Code
HDL based test bench and behavioral models
Test cases
Configurable synthesis shell
Documentation
Design Guide
Verification Guide
Synthesis Guide

Technical Specifications

Foundry, Node

GF 65LPe, GF 55LPe

Maturity

In Production

Availability

Immediate

GLOBALFOUNDRIES

In Production: 65nm LPe

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