The eDP 1.5 Verification IP provides an effective & efficient way to verify the components interfacing with the eDP interface of an ASIC/FPGA or SoC. The eDP VIP is fully compliant with Standard eDP Version 1.5 specifications from VESA This VIP is a lightweight VIP with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.
HDCP Verification IP
Overview
Key Features
- Supports HDCP 1.4, HDCP 2.2 and HDCP 2.3 end to end protection.
- Can handle HDCP encryption and decryption for 8 bit and 32 bit link symbol.
- Capable of continuous link integrity check for all lanes and rates.
- Supports aux transactions for authentication protocol.
- Supports encryption and decryption as per advanced encryption standard(AES).
- Capable of encryption and decryption with and without RS-FEC encoding/decoding.
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
- 24x5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover points with connectivity example for all the components
- Consistency of interface, installation, operation and documentation across all our VIPs
- Provide complete solution and easy
Block Diagram
Deliverables
- DisplayPort 1.4a BFM's for :
- Source - Link Layer
- Source - HDCP Encrypter
- Source - MAC Layer
- Source - PHY Layer
- Sink - Link Layer
- Sink - HDCP Decrypter
- Sink - MAC Layer
- Sink - PHY Layer
- Branching Devices
- LTTPR
- DisplayPort layered monitor & scoreboard
- Test Environment & Test Suite:
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Compliance Test Suite
- User Test Suite
- Integration Guide, User Manual and Release Note