HBM3 Memory Controller

Overview

Key Features

• High Bandwidth Memory (HBM) DRAM controller
• Supports AXI 4.0 port
• Supports DFI1: 2
• Supports BL8
• Supports AWORD/DWORD bus parity check
• Supports ECC & SEV
• Supports synchronous & asynchronous mode
• Supports pseudo channel mode; 32DQ per pseudo channel
• Supports configurable AXI Command/Data FIFO depths
• Supports AXI read interleaving
• Support programmable bit mapping
• Supports DBIac
• Supports manual self-refresh and auto self-refresh
• Supports BIST
• Support single bank Refresh
• Support up to 8.4 Gbps
• Support up to 32Gb per channel
• Support high-performance scheduling and QoS

Technical Specifications