HBM2 PHY for Samsung

Overview

Highest performance IP for graphics, AI/ML

Artificial intelligence (AI), high-performance computing (HPC), image processing, and autonomous driving applications generate and consume large volumes of data and require very high memory bandwidth. The Cadence® Denali® PHY IP for HBM2 for the Samsung 10LPP Process is an ideal solution for meeting these high-performance applications. The PHY IP for HBM2 is comprised of architectural improvements drawn from previous-generation DDR5 and LPDDR4 PHYs, achieving breakthrough performance, low energy per bit, and low area relative to the bandwidth provided. The PHY IP for HBM2 was developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoCs, and is verified with the Denali Controller IP for HBM2 as part of a complete memory subsystem solution.

Key Features

Lowest latency for data-intensive applications
Advanced clocking architecture minimizes clock jitter
Highest data rates with high-resolution delay adjust
Designed for optimized interposer routing
Memory controller interface uses DFI 4.0-like standard
DFI PHY Independent Mode for initialization and training
IEEE 1500 interface, BIST module, and loop-back function
Debug and bring-up software

Applications

Communications,
Consumer Electronics,
Data Processing,
Industrial and Medical,
Military/Civil Aerospace

Deliverables

GDS II macros with abstract in LEF
Verilog post-layout netlist
STA scripts for use at chip or standalone PHY levels
Liberty Timing model
SDF for back-annotated timing verification

Technical Specifications

Foundry, Node

Samsung 10nm

Maturity

Available on request

Samsung

Pre-Silicon: 10nm

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