HBM2E/HBM2 PHY

Overview

Highest performance IP for graphics, AI/ML

The High-Bandwidth Memory generation 2/2E PHY (HBM2E/2 PHY) is silicon-proven and is available in four process nodes: PHYs, achieving breakthrough performance, low energy per bit, and low area relative to the data bandwidth. It is engineered to quickly and easily integrate into SoCs and is verified as part of a complete memory subsystem solution. The HBM2E/2 PHY IP is an ideal solution for artificial intelligence (AI), high-performance computing (HPC), and image processing applications.

Key Features

Advanced clocking architecture minimizes clock jitter
DFI PHY Independent Mode for initialization and training
IEEE 1500 interface, Memory BIST feature, and loop-back function
Designed for optimized interposer routing
Pin programmable support for lane repair

Block Diagram

Applications

Communications,
Consumer Electronics,
Data Processing,
Industrial and Medical,
Military/Civil Aerospace

Deliverables

GDS II macros with abstract in LEF
Verilog post-layout netlist
STA scripts for use at chip or standalone PHY levels
Liberty Timing model
SDF for back-annotated timing verification

Technical Specifications

Foundry, Node

Samsung 10nm

Maturity

Available on request

Samsung

Pre-Silicon: 10nm

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