HBM2 Memory Controller

Overview

Key Features

• Support Pseudo Channel mode with 64DQ per Pseudo Channel
• Support DFI1:1
• Support HBM Burst Length 4
• Support 4 High or 8 High HBM Devices
• Support only 1 AXI 4.0 ports with 128-bit data bus width for each Pseudo channel
• Support only AXI burst type = INCR, AXI burst length = 8, AWSize/ARSIze = 3’h4 (128-bit), and AWAddr/ARAddr is 128-Byte aligned
• Support only Parity Latency = 0 or 2
• Support Read DBI and Write DBI features
• Support Command/Address parity check feature
• Support DQ parity check feature
• Support both mode-1 and mode-2 DWORD remapping features
• Support HBM ECC function
• Support internal SRAM ECC function
• Support AXI read interleaving
• Consistent AXI read-after-write
• Support software programmable mapping from AXI address to SID, Bank-Group, Bank, Row, Column bits for user specific applications
• Support manual self-refresh and automatic self-refresh
• Support manual power-down and automatic power-down
• Support single bank refresh
• Support auto precharge
• Support memory BIST (Built In Self Test) function

Technical Specifications