H.264 UHD Hi422 Intra Video Decoder

Overview

The AL-H264D-4KI422-HW is a hardware-based, feature rich, low latency, high video quality H.264 (AVC) UHD Hi422 Intra decoder IP core. The AL-H264D-4KI422-HW decoder pairs up with the Atria Logic AL-H264E-4KI422-HW low latency encoder for low latency end-to-end links.

The decoder is targeted for medical imaging, broadcast, enterprise/CE and industrial applications. Medical imaging applications include endoscopy, micro surgery and remote assisted surgery and diagnostics. Broadcast applications include video recorders for news and event coverage, film sets and production studios, as well as real-time monitoring of video shoots. Enterprise/CE applications include HDBaseT video transmission over CAT5/6 Ethernet cabling to computer monitors and UHD TV displays. Industrial applications include monitoring of manufacturing plants, and remote manipulation of mobile or fixed light or heavy machinery.

The decoder supports the H.264 Hi422 (High-422) profile at Level 5.1 (3840x2160p30) for Intra-only coding. Support for 10-bit video content means that there is no degradation of grayscale or color gradients in terms of banding. Support for YUV 4:2:2 video content means that there is better color separation, especially noticeable for red colors, which provides much sharper image details. These video quality aspects are especially important in case of medical imaging applications.

Support for Intra-only decoding allows the decoder to decode compressed video at frame latencies. A macroblock-line level pipelined architecture brings the latency further down to sub-frame level, at about 0.3msec. When connected to the Atria Logic AL-H264E-4KI422-HW low latency encoder via an IP network, the glass-to-glass latency is about 0.6msec, not taking into account any transmission latency, and otherwise 2 frames with transmission in case of an IP network. Such low latency is important for any closed-loop man-machine application as mentioned here above

The decoder is implemented in a single Xilinx Zynq-7000 XC7Z045 all programmable SoC. The efficient implementation only takes up 38% of the programmable logic resources, 10% of available DSP resources, and 19% of the available RAM, leaving ample room for implementation of any other required circuitry. Integration of a Gb Ethernet MAC provides streaming over IP support.

Key Features

  • H.264 Intra-only Hi422 Level 5.1 decoding
  • 8/10-bit support
  • YUV 4:2:2 support
  • Very low latency at ~0.3sec
  • Variable bit rate (VBR) and constant bit rate (CBR) support
  • Gb Ethernet streaming input support
  • Xilinx Zynq-7000 XC7Z045 SoC implementation

Benefits

  • Very low latency
  • High video quality
  • UHD resolution
  • Low power
  • Spare on-chip programmable logic and RAM
  • FPGA or ASIC implementations

Block Diagram

H.264 UHD Hi422 Intra Video Decoder Block Diagram

Applications

  • Medical imaging
  • Video recorders for broadcast and film
  • HDBaseT video over CAT5/6
  • Remote monitoring
  • Remote manipulation of machinery

Deliverables

  • The package includes all the files required for programming and testing Atria Logic 4K Decoder on Zynq706 board.
  • Contents of Decoder_4K.rar (within 4k_Dec_Package.rar downloaded from DropBox)
    • SD card content
      • Bin - It has elf executables of 4k decoder
      • Bitstream - It has encoded video input stream to 4k decoder
      • boot.bin - Bootable binary file on Zynq SoC
      • devicetree.dtb - Zynq7000 SoC device Tree
      • uImage - Linux Kernel Image
      • uramdisk.image.gz - Linux Root file system
      • Dec_4k_SD_Card.sh - Script to run the 4k decoder on zynq ZC706 board
    • Format conversion folder contents (copy this folder into Linux Machine)
      • txt2bin.c - This file has to be compiled and run to convert Raw video txt file into binary
    • Reference documents
      • H264_HW_Codec_User_Guide.pdf
      • PREPARING_SD_CARD_FOR_ATRIALOGIC_CODEC.pdf
      • 7yuv_player.pdf
    • ReadMe.txt - This text file describes the files and directory structure of Decoder_4K.rar and demo setup details

    Technical Specifications

    Maturity
    Prototype
    Availability
    2 months
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Semiconductor IP