H.264 CODEC FPGA Core
Overview
Our FPGA core is highly optimized and 80% SMALLER THAN THE COMPETITION! It is capable of being synthesized in Xilinx FPGAs and supports H.264 variable and fixed bit-rate encoding of video streams. Encodes video data at 1.5 clocks/pixel. Typical clock rate in an Xilinx SPARTAN 6 is 95Mhz. Typical clock rate in a Xilinx Zynq 7020 is 95MHz. Multiple cores can be used for processing larger size or higher frame rate images. Uses FPGA specific DDR 3 controller and microprocessor soft core. In addition, the standard core can be customized, retaining ITAR compliance, to meet unique functional needs.
Key Features
- Designed for high-speed, high-pixel count CMOS sensors interfacing to medium to high-bandwidth connections
- 1.5 clocks/pixel processing rate
- Built in H.264 Decoder that can decode A2e specific H.264 encoded streams
- Fully compatible with the ITU-T H.264 specification
- Supports resolutions up to 4096 x 4096 (can be expanded with additional cores)
- Supports simultaneous encoding of multiple streams of arbitrary sizes and compression ratios
- Generates I and P frames
- Variable Bit Rate (VBR) and Constant Bit Rate (CBR)
- Search range: 80 X 48 pixels, Full, 1/2, 1/4 pixel resolution
- Entropy Encoding: CAVLC-
- Support for intra 4 x 4 DC prediction
- Support for Single or Multiple slices via firmware control
- Supports YUV 4:2:0 video input
- Fully synchronous design
- Available as FPGA specific netlist
- Custom versions available
Deliverables
- Binary or source code licenses available
Technical Specifications
Availability
Available Now