GTS PMA/FEC Direct PHY IP

Overview

GTS is a general purpose transceiver in Agilex™ 5 and Agilex™ 3 FPGAs. The transceiver is monolithically integrated into the FPGA core fabric offering up to 28Gbps for Agilex™ 5 and up to 12.5Gbps data speeds for Agilex™ 3 FPGA. The transceiver is optimized for power efficiency, low-latency, and dynamic reconfiguration to implement multiple protocols.

*Only in Agilex™ 5 FPGA E-Series Group A and D-Series devices

**Only in Agilex™ 3 FPGA C-Series

Key Features

  • Dynamic Reconfiguration - NRZ transceivers optimized for a wide variety of applications, ranging from 1 Gbps to 28.1 Gbps* and 1 Gbps to 12.5Gbps**
  • Advanced adaptive equalization circuits to enable long-reach backplane driving applications.
  • Dedicated PMA and PLLs for independent usage of transceiver channels with Avalon® memory-mapped interface.
  • Hardened PCS—supports 64b/66b encoding and decoding functions, data scrambling, block alignment, and gear boxing functions.
  • Hardened FEC—Firecode and Reed Solomon for 10/25 Gb Ethernet BASE-KR/CR (Backplane) applications.
  • Supports SFP and SFP+ Direct Attach for implementation of optical modules.
  • Supports PCIe 4.0 x8*, PCIe 3.0 x4**, 25Gb Ethernet*, and 10Gb Ethernet** with IEEE 802.3 compliant, and FEC – Firecode and Reed Solomon.

Block Diagram

GTS PMA/FEC Direct PHY IP Block Diagram

Applications

  • 100/200 Gbps OTN Muxponders and 2.5Gbps – 100Gbps GPON Platform.
  • Solid State Radar Platforms.
  • Low Latency Ethernet Network Interfaces.
  • High-Bandwidth PCIe interfaces.
  • HD video and vision processing.

Technical Specifications

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Semiconductor IP