General-Purpose I/O (GPIO) - 1.5V-1.8V

Overview

The 1.8V General Purpose I/O libraries provide bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power cells along with the necessary support cells to construct a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.

Key Features

? Multi-Voltage (1.2V, 1.5V, 1.8V)
? LVCMOS / LVTTL input with selectable hysteresis
? Programmable drive strength (rated 2mA to 12mA)
? Selectable output slew rate
? Optimized for EMC with SSO factor of 8
? Open-drain output mode
? Programmable input options (pull-up/pull-down/repeater)
? Power-On Start (POS) capable
? Power sequencing independent design with Power-On
Control

Deliverables

a. Physical abstract in LEF format (.lef)
b. Timing models in Synopsys Liberty formats (.lib and .db)
c. Calibre compatible LVS netlist in CDL format (.cdl)
d. GDSII stream (.gds)
e. Behavioral Verilog (.v)
f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
g. Databook (.pdf)
h. Library User Guide - ESD Guidelines (.pdf)

Technical Specifications

Foundry, Node

TSMC 16nm

Maturity

Silicon Proven

Availability

Available Now

GLOBALFOUNDRIES

In Production: 130nm
Pre-Silicon: 130nm
Silicon Proven: 28nm HPP , 28nm LPH , 28nm SLP

TSMC

In Production: 90nm G , 130nm G
Pre-Silicon: 90nm G , 130nm G

UMC

In Production: 130nm
Pre-Silicon: 130nm

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General-Purpose I/O (GPIO) - 1.5V-1.8V

Overview

Key Features

Deliverables

Technical Specifications

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