IP Catalog > Memory Controller/PHY IP > GDDR IP > GDDR5X DFI Verification IP

GDDR5X DFI Verification IP

Overview

GDDR5X DFI Verification IP provides an smart way to verify the GDDR5X DFI component of a SOC or a ASIC. The SmartDV's GDDR5X DFI Verification IP is fully compliant with standard DFI Specification and provides the following features.

GDDR5X DFI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

GDDR5X DFI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Compliant with DFI version 4.0 or 5.0 Specifications.
  • Supports GDDR5X devices compliant with JEDEC GDDR5X SGRAM Standard JESD232 and JESD232A.
  • Supports all Interface Groups.
  • Supports Write Transactions with Data mask.
  • Supports DRAM Clock disabling feature.
  • Supports Data bit enable/disable feature.
  • Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
  • Supports frequency change protocol.
  • Supports Low power control features.
  • Supports Error signaling.
  • Supports DFI Read/Write Chip Select.
  • Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays.
  • Constantly monitors DFI behavior during simulation.
  • Protocol checker fully compliant with DFI 4.0 or 5.0 Specifications.
  • Bus-accurate timing for min, max and typical values.
  • Notifies the test bench of significant events such as transactions, warnings.
  • Built in functional coverage analysis.
  • Supports callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster test bench development and more complete verification of GDDR5X DFI designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

GDDR5X DFI Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the GDDR5X DFI testcases.
  • Complete UVM/OVM sequence library for GDDR5X DFI controller.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all classes, tasks and functions used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info

Related IPs

×
Semiconductor IP