GDDR5 Memory Model

Overview

GDDR5 Memory Model provides an smart way to verify the GDDR5 component of a SOC or a ASIC. The SmartDV's GDDR5 memory model is fully compliant with standard GDDR5 Specification and provides the following features. Better than Denali Memory Models.

GDDR5 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

GDDR5 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports GDDR5 memory devices from all leading vendors.
Supports 100% of GDDR5 protocol standard JESD212C.
Supports all the GDDR5 commands as per the specs.
Quickly validates the implementation of the GDDR5 standard JESD212 and JESD212C.
Supports for programmable clock frequency of operation.
Supports for all types of timing and protocol violation detection.
Supports up to 8GB device density.
Supports the following device modes.

Supports for All Mode register programming.
Checks for following

Check-points include power on, Initialization and power off rules,
State based rules, Active Command rules,
Read/Write Command rules etc.
All timing violations.

Supports for Single ended interface for command, address and data.
Supports Double Data Rate (DDR) data (WCK).
Supports Single Data Rate (SDR) command (CK).
Supports Double Data Rate (DDR) addressing (CK).
Supports for Programmable Burst length 8.
Supports for Programmable read latency and write latency.
Supports for Write data mask function via address bus.
Supports for Data bus inversion (DBI) & address bus inversion (ABI).
Supports for Input/output PLL/DLL.
Supports for Address training.
Supports for cyclic redundancy check (CRC-8).
Supports for Programmable CRC read latency, write latency.
Supports for Low Power modes.
Supports for Auto & self-refresh modes.
Supports for Auto Precharge option for each burst access.
Supports for On-die termination (ODT) for all high-speed inputs.
Supports for input clock stop and frequency change.
Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Protocol checker fully compliant with GDDR5 Specification JESD212 and JESD212C.
Constantly monitors GDDR5 behavior during simulation.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of GDDR5 designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the GDDR5 testcases.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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