Frac-N PLL on Samsung 28nm LN28FDS

Overview

PLL2860X is a 1.8V/1.0V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.

It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).

Key Features

  • Dual power supply of 1.8V±10% and 1.1V+5% ~1.0V-10% 
  • Operating junction temperature(TJ): -40°C ~ 125°C 
  • Output frequency range: 19.5MHz ~ 2.5GHz 
  • Duty ratio: 45 ~ 55% 
  • Power down mode 
  • Bypass mode (FOUT = FIN) 
  • Programmable dividers 
  • Glitch-free scaler 
  • On-chip loop filter

Benefits

  • Glitch-free scaler
  • Low Jitter
  • Low Power

Block Diagram

Frac-N PLL on Samsung 28nm LN28FDS Block Diagram

Applications

  • Mobile/Consumer

Deliverables

  • FE(Front-End) : LEF, LIBERTY, MODEL, TB FUNCTION
  • BE(Back-End) : CIR, DFM, DRC, GDS, LVS

Technical Specifications

Short description
Frac-N PLL on Samsung 28nm LN28FDS
Vendor
Vendor Name
Foundry, Node
SF 28nm, LN28FDS
Samsung
Pre-Silicon: 28nm FDS
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Semiconductor IP