Foundry sponsored - Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k

Overview

Foundry sponsored - Single port SRAM compiler - TSMC 55 nm uLP - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 kbits

Key Features

  • FOUNDRY SPONSORED
  • HIGHEST DENSITY
  • -Smart periphery design
  • -Typically up to 20% gain in density versus alternative HD-LP RAM depending on instance configuration
  • -Uses Pushed Rules Foundry bitcell
  • EXTENDED BATTERY LIFE
  • -Designed with partitioned array to reach ultra low power consumption from 1.2 V +/-10% downto 0.9 V +/-10%
  • -Available power saving modes: stand-by mode and data retention mode
  • -Minimum data retention mode for ultra low leakage savings: 0.55 V (optional)
  • EASIEST INTEGRATION
  • -MUX option enabling several performance trade-offs and form factors
  • -Data range flexibility allows easy addition of bits for ECC purposes
  • -Address range flexibility allows easy addition of single rows for redundancy purposes
  • ENABLES RIGHT ON FIRST PASS DESIGN
  • -Complete mismatch validation of the memory architecture taking into account local and global dispersion
  • -Extended validation for a high coverage rate of the compiler

Technical Specifications

Maturity
In_Production
TSMC
In Production: 55nm ULP
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Semiconductor IP