The KA13ETHB33 is a single-port PHY with an MII (Media Independent Interface). It implements all 10/100M Ethernet Physical- layer functions including the Physical Coding Sub-layer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent sub-layer (TP-PMD), 10Base-Tx Encoder/Decoder, and Twisted Pair Media Access Unit (TPMAU).
Ethernet 10/100 PHY
Overview
Key Features
- Supports MII.
- Auto-MDX
- 10/100Mbs operation supported
- Full/half duplex operation
- Twisted pair output only
- Supports Base Line Wander (BLW) compensation
- Adaptive Equalization
- 25MHz crystal/oscillator as clock source
- IEEE 802.3/802.3u compliant including auto- negotiation
- 0~125°C junction temperature
- Silterra 130nm CMOS process
Benefits
- With on-chip DSP (Digital Signal Processing) technology, the chip provides excellent performance under all operating conditions.
Block Diagram
Applications
- Network Interface Adapters
- Ethernet Hubs/Switches
- ADSL/Cable Modems
- VoIP Phone Sets
Deliverables
- Data Sheet
- Test Documentation
- Integration Guide
- GDSII
- LVS netlist
- LEF model
- Verilog Model
- Timing Model
Technical Specifications
Foundry, Node
Silterra 130nm
Maturity
Silicon Proven
Availability
NOW