eMMC Device Controller IIP

Overview

eMMC DEVICE interface provides full support for the eMMC DEVICE synchronous serial interface, compatible with JESD84-B51 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. eMMC DEVICE IIP is proven in FPGA environment. The host interface of the eMMC can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

eMMC Device Controller IIP is supported natively in Verilog and VHDL

Key Features

Compliant with JESD84-B51 Specification and earlier versions
Compliant with JEDEC eMMC CQHCI for Command Queuing
Supports different data bus width modes : 1-bit, 4-bit, 8-bit.
Supports Command queuing
Supports Enhanced Strobe
Supports higher than 2GB densities of memory.
Supports Replay Protected Memory Block(RPMB) functionality.
Supports packed Write/Read commands.
Supports High Priority Interrupt (HPI) Mechanism
Supports send tuning block(CMD21) command.
Supports Single and Dual Data Rate Timing for Read/Write Operations
Supports HS200 and HS400 Modes.
Supports Single byte, Single block ,Multi –block(finite and infinite) transfers and MMC
Supports CRC7 checking for command and CRC16 for Data integrity
Supports Password protection for Cards
Supports extended security protocols commands.
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

Single site license option is provided to companies designing in a single site.
Multi sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The eMMC DEVICE Controller is available in Source and netlist products.
The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.

Technical Specifications

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