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EDORAM Memory Model

Overview

EDORAM Memory Model provides an smart way to verify the EDORAM component of a SOC or a ASIC. The SmartDV's EDORAM memory model is fully compliant with standard EDORAM Specification and provides the following features. Better than Denali Memory Models.

EDORAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

EDORAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Supports EDORAM memory devices from all leading vendors.
  • Supports 100% of EDORAM protocol standard.
  • Supports all the EDORAM commands as per the specs.
  • Supports up to 16MB device density.
  • Supports the X16 device mode operation.
  • Supports Auto refresh interval as 1024 cycles/16ms.
  • Supports Self refresh interval as 1024 cycles/128ms.
  • Supports for following Refresh Mode:
    • RAS-Only
    • CAS-before-RAS (CBR)
    • Hidden
  • Checks for following
    • Check-points include power up, initialization and power off rules
    • State based rules, Active Command rules
    • Read/Write Command rules etc.,
    • All timing violations
  • Supports the Byte Write and Byte Read operation via two CAS.
  • Supports for full-timing as well as behavioral versions in one model.
  • Supports for all timing delay ranges in one model: min, typical and max.
  • Constantly monitors EDORAM behavior during simulation.
  • Protocol checker fully compliant with EDORAM Specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Benefits

  • Faster testbench development and more complete verification of EDORAM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

EDORAM Memory Model Block Diagram

Deliverables

  • Complete regression suite containing all the EDORAM testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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