eCPRI

Overview

Size optimized, silicon agnostic IP core suitable for line rates upto 25G

eCPRI core is a highly scalable and silicon agnostic implementation of the eCPRI standard targeting any ASIC or FPGA technologies. The eCPRI implementation builds on Chip Interfaces long-time experience designing CPRI and Radio-Over-Ethernet solutions for fronthaul and delivers a flexible engine that is prepared for tight integration with software applications.

The IP is designed to meet or exceed the requirements of radio systems, base band systems, fronthaul switches or advanced test systems. The speed optimized core can handle any solutions reaching from the “small footprint” to the most complex applications running 25 Gbps. The IP can dynamically be configured to handle wireless multi- mode radio systems enabling high-performance throughputs required by 4G and 5G wireless solutions.

Key Features

  • Delivering Performance
    • Supporting small to large system configurations
    • Support for frequency-domain IQ transport
    • Support for various functional split between RU and BBU
    • Supports 10G/25G Ethernet MAC ports
    • Agnostically supports multiple synchronization schemes
    • Wide flexibility for configuring
  • Easy to use
    • Testbench with typical system configuration and examples
    • Easy integration
  • Silicon Agnostic
    • Targeting both ASICs and FPGAs

Benefits

  • Test Environment: CPRI 7.0 IP is tested against a VIP model in UVM regression for full functional coverage
  • Silicon Agnostic: Optimized for ASIC but can be synthesized for most FPGAs
  • Interoperability Tested: Multiple field deployments and tested against CPRI references
  • Radio Expertise: IP with rich feature set designed by pioneers in radio solutions
  • Active Support: All support is actively provided by engineers directly

Block Diagram

eCPRI Block Diagram

Deliverables

  • The IP Core can be delivered in Source code or Encrypted format.
  • The following deliverables will be provided with the IP Core license:
    • Solid documentation, including User Manual and Release Note.
    • Simulation Environment, including Simple Testbed, Test case, Test Script.
    • Access to support system and direct support from Comcores Engineers.

Technical Specifications

×
Semiconductor IP