The demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to control the operation, and can be externally configured via the SPI interface.
This design is a DVB-T2 OFDM demodulator, supplied as a portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner.
QAM signal constellations are supported, including QAM16, QAM64 and QAM256. QPSK, and BPSK are also supported. The operation of the demodulator is automated by a master finite state machine.
The LDPC block and the BCH decoder deal with short frame and normal frame types. The LDPC decoder decodes iteratively following the
minimum-sum algorithm. The BCH decoder can correct up to 12 bits, or 10 bits per code-word, depending on the frame type and coding rate. The other two BICM chains are used for signaling and parameter passing.
DVB-T2 Demodulator and LDPC/ BCH Decoder
Overview
Key Features
- DVB-T2 EN302 755 V1.2.1, Rev.9 compliant
- Supports IF input
- Single input – Single output (SISO)
- Sampling frequency offset (SFO) tracking and compensation
- Carrier frequency offset (CFO) detection and correction
- Flexible channel BW (1.7, 5, 6, 7, 8, and 10) MHz
- BPSK, QPSK, QAM constellations 16, 64, and 256
- Channel BW (1.7, 5, 6, 7, 8, and 10) MHz
- Soft demodulation
- FFT size (1, 2, 4, 8, 16, and 32) K
- Guard interval (1/128, 1/32, 1/16, 19/256, 1/8, 19/128, and 1/4) cessor
- Coding rate (1/2, 3/5, 2/3, 3/4, 4/5, and 5/6)
- Short and long frames
- Layered Min-Sum LDPC decoder
Benefits
- The design interfaces to an external Analog to Digital converter, which receives the analog signal from the external tuner. The included carrier frequency offset (CFO) correction can compensate up to 500KHz for 8MHz channel bandwidth. The timing correction loop can correct mismatches as large as 50ppm depending on the FFT size and QAM constellation.
Applications
- Set-top boxes
- Digital TV Receivers
Deliverables
- Synthesizable Verilog
- System Model (Matlab) and Documentation
- Verilog Test Benches
- FPGA testing environment
Technical Specifications
Maturity
silicon proven
Availability
immediately