DVB-S2/S Demodulator and Decoder IP (Silicon Proven)

Overview

The DVB-S2/S Demodulator IP core is a silicon-proven IP core extracted from Production chips. It contains tuner Rx gain control which makes PDM Demodulator a high performance (A)PSK output Rx at AGC. Further stages of gain control are demodulator core intended for DVB-S2 and DVB-S implemented digitally within the demodulator. forward link applications. The demodulator is compatible with the ACM, VCM, and CCM configurations of the DVB-S2 Standard including DVB-S extensions and is therefore suitable for the reception of DVB broadcast, DSNG, professional and broadband interactive services.

DVB-S and S2 demodulation:
Compliant with ETSI EN300421 and EN302307
Symbol rates from 1 to 45 Ms/s
Enhanced FEC for DVB-S and DirecTV legacy transmissions

Key Features

  • Compatible with all ACM (Adaptive Coding and Modulation), VCM (Variable Coding and Modulation) and CCM (Constant Coding and Modulation) configurations of ETSI EN 302 307-1 and ETSI EN 302 307-2.
  • Frame-by-frame selection of frame size, FEC code rate and modulation format (QPSK, 8PSK, 16APSK and 32APSK).
  • Support for DVB-S2 extensions (S2X) FEC code-rates and modulation formats (64APSK, 128APSK and 256APSK)
  • Support for an arbitrary range of symbol rates up to 40% of the master clock frequency
  • Two-stage, stepped carrier search provides wide acquisition range
  • Integrated, high-performance pi/2-BPSK demodulator and Reed Muller FEC decoder for Frame Header processing (PLSCODE).
  • Baseband I/Q radio interface incorporating compensation for DC offset and quadrature imbalances
  • Pilot-assisted carrier tracking ensures robust performance in the presence of high levels of phase noise.
  • PL sync acquisition and maintenance at – 2dB SNR (Es/N0)
  • Digital decimation and channel filters reject up to +10dBc of adjacent channel interference.
  • Fully-digital carrier and clock recovery circuits eliminate the need for an external VCXO.
  • Compatible with leading LDPC FEC decoder solutions.
  • Supplied as a protected bitstream or netlist (Megacore® for Altera® FPGA targets).

Benefits

  • Silicon Proven IP Core
  • Extracted from Production Chips
  • Multiple applications
  • Modification rights, unlimited usage
  • Ready to License
  • Fully Packaged
  • Modifications Rights

Block Diagram

DVB-S2/S Demodulator and Decoder IP (Silicon Proven) Block Diagram

Applications

  • STB SOC
  • TV SOC
  • PCTV Dongle etc

Deliverables

  • Verilog Source RTL Code plus Simulation Environment
  • C Source Code
  • Physical Design scripts - Synopsys synthesis
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers

Technical Specifications

Foundry, Node
TSMC, SMIC, FDSOI
Maturity
In Production
Availability
Ready to license
×
Semiconductor IP