The CMS0048 DVB-S/DSNG Demodulator is a high-performance (A)PSK demodulator core intended for DVB-S and DVB DSNG forward link applications.
The demodulator provides soft-constellation outputs together with recovered QAM information suitable for decoding by the integrated DVB-S/DSNG FEC decoder. The TS output stream is smoothed before being output from the core.
Operating symbol rate is programmed from a software register and extends from approximately 40% of the master clock frequency down to an arbitrary low rate that is set through synthesis options. The range would normally be dictated by the application and, in particular, the phase noise characteristics of the radio system.
Carrier acquisition is performed in several stages starting with a coarse, stepped search. The search range and step size are programmed through software registers and can be set to accommodate an arbitrary offset (within the sample rate bandwidth).
Constellation symbols are output as soft decisions after the recovery of carrier phase, symbol timing and gain.
The CMS0048 is provided with a baseband I/Q radio interface compatible with zero-IF and near zero-IF tuner modules. The interface performs automatic compensation of DC offsets and quadrature imbalances (phase and amplitude).
Tuner Rx gain control is provided through either PDM or parallel gain value outputs. Further stages of gain control are implemented digitally within the demodulator.
The Decimation Filter stage suppresses wideband interference and restricts the sample rate bandwidth prior to matched (RRC) channel filtering and timing recovery. The combined response of the Decimation and Channel Filters allows the CMS0048 to tolerate up to +10dBc of adjacent channel interference at any supported symbol rate.
A single processor at the output of the Channel Filter handles the DVB-S/DSNG demodulation functions – primarily carrier and phase recovery.
The carrier-recovery block corrects the phase and frequency offsets for QPSK, 8-PSK or 16-QAM constellations before delivering soft outputs symbols (unsliced constellation samples) for either external decoding, or to the integrated FEC decoder.
Register Configuration
Static configuration and status monitoring is performed through a bank of registers. This would typically be driven from a processor interface connected to a CPU that is embedded on the same device or located off-chip. Parameters accessible through this interface include:
- Nominal symbol and input carrier frequencies;
- Window and step sizes for the coarse carrier search;
- AGC and PLL configuration and status;
- Estimated signal-to-noise ratio (CNIR).
Important synchronisation events such as the acquisition of symbol timing lock are signalled through the SyncEvents output. Some or all of these signals would typically be connected to the processor interface as sources of interrupt but might otherwise be polled as status indicators.
The Channel and Decimation Filters use hard-wired FIR filter coefficients that are generated during synthesis. FPGA platforms employing more than one Channel Filter configuration would normally store a different netlist for each filter used.
The option of programmable coefficients is available for ASIC and high-end FPGA platforms that have adequate (multiplier) resources.
Full details of the register interface are provided in the CMS0048 IP Guide document.
