IP Catalog > DSP & Math IP > Modulation/Demodulation IP > DVB IP Core > DVB-C demodulator / J83 demodulator

DVB-C demodulator / J83 demodulator

Overview

The CMS0022 DVB-C/J.83 Cable Demodulator is a 4th generation design that exploits the vendor’s experience of QAM and OFDM systems for broadband terrestrial, satellite and cable modems.

The core forms an integrated cable demodulator solution comprising of the Universal QAM Demodulator(CMS0006) and J.83abc/DVB-C Cable FEC Decoder(CMS0018) cores.

The core has been designed to lock robustly in the presence of noise, frequency & timing offsets, static & dynamic multi-path channels and various other forms of interference. The demodulator core consists of four major sub-modules: the Radio interface & decimator, Symbol timing recovery, Equaliser and the FEC Decoder.

The operation of the demodulator is fully automated by an internal state machine.

Key Features

  •  
  • DVB-C EN 300 429
  • ITU J83 Annexes A/B/C
  • DOCSIS 1.1 / 2.0
  • IF sub-sampling or I/Q baseband interface.
  • Standard 188-byte MPEG Transport Stream output.
  • Variable ADC width support.
  • Single external clock source required.
  • Single external analogue loop for AGC.
  • Fully digital and automatic timing & frequency recovery - no VCXO or AFC required.
  • Fully-digital matched channel filter for robust performance in the presence of ACI.
  • Automatic QAM mode, FEC and spectral inversion searching.
  • Pre-Viterbi and Pre-RS bit-error-rate (BER) statistics.
  • Post-FEC bit-error-rate (BER) statistics.
  • Blind and decision-directed adaption algorithms ensure rapid convergence of AGC, PLL and equaliser sub-systems.
  • Automatic channel equalisation using LTE and DFE algorithms - signal quality estimate available.
  • Symbol rate recovery up to approximately 40% of the master clock frequency.
  • Full DVB-C/J83 QAM support: 16, 32, 64, 128, 256
  • Implementation loss of <1dB for 128 or 256-QAM, and <0.5dB for other supported QAM modes.
  • External RAM interface for long interleave modes.
  • Number of debug signals available - carrier, timing lock, frequency offset etc.
  • Supplied as a protected bitstream or netlist (Megacore for Altera FPGA targets).

Block Diagram

DVB-C demodulator / J83 demodulator Block Diagram

Technical Specifications

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