DDR4/LPDDR4/LPDDR4X PHY

Overview

Key Features

• Multi-interface support. LPDDR4 up to 3200Mbps and DDR4/LPDDR4X up to 4267Mpbs.
• Support LPDDR4X 0.6V VDDQ.
• Optimized for high performance and flexibility for integration. The harden IP included 8bit data blocks, 6bit C/A blocks, clock blocks, PLL, and DLL. The IP pinout can be configured to optimize for LPDDR4/4X and DDR4.
• High resolution read/write timing control.
• Per bit deskew on reading/write data path.
• Multiple PHY independent training modes. Including periodic background training.
• Low power mode.
• Dynamic frequency scaling.
• Testability support: Scan, ATPG with OPCG, BIST with loop backtest.
• Advanced equalization, include TX FFE and RX DFE.
• PI/SI design guidelines to guarantee high data rate performance.
• Advance clock structure to minimize jitter and automated interface timing margining.

Technical Specifications