DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process
Overview
DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process
Technical Specifications
Foundry, Node
UMC 65nm
Maturity
Silicon proven, Formal release
UMC
Pre-Silicon:
65nm
LL
,
65nm
LP
,
65nm
SP
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