DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process
Overview
DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process
Technical Specifications
Short description
DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process
Vendor
Vendor Name
Foundry, Node
UMC 65nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
65nm
LL
,
65nm
LP
,
65nm
SP
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