DDR/LPDDR PHY

Overview

LPDDR5X, LPDDR5, LPDDR4X, LPDDR4, LPDDR3 PHY and Controller

The DDR/LPDDR PHY IP, a family of high-speed on-chip interface IP, provides the industry's highest data rates combined with low-latency throughput while balancing power consumption and minimizing area. The DDR/LPDDR PHY and Controller IP are developed and validated to reduce risk for the customer so that their SoC will work right the first time. Available as a product-optimized solution for specific applications such as DDR5/LPDDR5, DDR4/LPDDR4, DDR3/LPDDR3, and additional multiple protocol combinations.

Key Features

DDR5/4/3 training with write-leveling and data-eye training
Optional clock gating available for low-power control
Internal and external datapath loop-back modes
I/O pads with impedance calibration logic and data retention capability
Programmable per-bit (PVT compensated) deskew on read and write datapaths
RX and TX equalization for heavily loaded systems

Benefits

Multi-protocol Solution: DDR and LPDDR supported in a single IP
Highly Configurable: Application-specific parameters and floorplan optimization
Low Power and Area: Industry-leading PPA based on advanced architecture and implementation
Low Latency: For data-intensive applications
Reliable: Maximum system margin with advanced clocking and I/O architectures
Future proof: Cutting edge technology with the latest GDDR protocols and the highest data rates

Block Diagram

Technical Specifications

Foundry, Node

TSMC 5nm

Maturity

Available on request

TSMC

Pre-Silicon: 5nm

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