DDR/LPDDR PHY

Overview

LPDDR5X, LPDDR5, LPDDR4X, LPDDR4, LPDDR3 PHY and Controller

The DDR/LPDDR PHY IP, a family of high-speed on-chip interface IP, provides the industry's highest data rates combined with low-latency throughput while balancing power consumption and minimizing area. The DDR/LPDDR PHY and Controller IP are developed and validated to reduce risk for the customer so that their SoC will work right the first time. Available as a product-optimized solution for specific applications such as DDR5/LPDDR5, DDR4/LPDDR4, DDR3/LPDDR3, and additional multiple protocol combinations.

Key Features

DDR5/4/3 training with write-leveling and data-eye training
Optional clock gating available for low-power control
Internal and external datapath loop-back modes
I/O pads with impedance calibration logic and data retention capability
Programmable per-bit (PVT compensated) deskew on read and write datapaths
RX and TX equalization for heavily loaded systems

Block Diagram

Applications

Communications,
Consumer Electronics,
Data Processing,
Industrial and Medical,
Military/Civil Aerospace

Deliverables

GDS II macros with abstract in LEF
Verilog post-layout netlist
STA scripts for use at chip or standalone PHY levels
Liberty timing model
SDF for back-annotated timing verification

Technical Specifications

Foundry, Node

TSMC 5nm

Maturity

Available on request

TSMC

Pre-Silicon: 5nm

Request Info