DDR/LPDDR Controller

Overview

LPDDR5X, LPDDR5, LPDDR4X, LPDDR4, LPDDR3 PHY and Controller

The DDR/LPDDR PHY IP, a family of high-speed on-chip interface IP, provides the industry's highest data rates combined with low-latency throughput while balancing power consumption and minimizing area. The DDR/LPDDR PHY and Controller IP are developed and validated to reduce risk for the customer so that their SoC will work right the first time. Available as a product-optimized solution for specific applications such as DDR5/LPDDR5, DDR4/LPDDR4, DDR3/LPDDR3, and additional multiple protocol combinations.

Key Features

Sideband and in-line SEC/DED ECC
Supports advanced RAS features including error scrubbing, parity, etc.
Compliant to LPDDR5/4X/4/3 and DDR5/4/3 protocol memories
Memory controller interface complies with DFI standards up to version 5.0
Priority per command on Arm^® AMBA^® 4 AXI, AMBA 3 AXI
Single and multi-port host interface options
QoS features allow command prioritization on Arm AMBA 4 AXI and CHI interfaces
Silicon proven and shipping in volume

Block Diagram

Applications

Data Processing

Deliverables

Clean, readable, synthesizeable Verilog RTL
Synthesis and STA scripts
Documentation—integration and user guide, release notes
Sample verification testbench with integrated BFM and monitors

Technical Specifications

Maturity

Silicon proven

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