CXL 2.0 Retimer
Overview
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retimer. An important capability of a Physical Layer protocol aware Retimer is to execute the Phase 2/3 of the equalization procedure in each direction. Compliant with pipe specification.
Key Features
- Compliant with CXL 2.0 spec.
- Compliant with PCIE Gen5/4 Specs.
- Forward mode supported.
- X1,X2,X4,X8,X16 lanes supported.
- Lane bifurcation supported.( X16, X8X8, X4X4X4X4, X1)
- PIPE 40bit Serdes interfaces.
- APB interface for register configurations.
- Lane deskew supported.
- Support for L1 states.
- SKP OS add/removal.
- SRIS mode supported.
- Deemphasis negotiation support at 5GT/s.
- EI inferences in all modes.
- Automatic adjustment of data rates in conjunction with upstream and downstream devices.
- Automatic adjustment of link width in conjunction with upstream and downstream devices.
- Scrambling, descrambling Support.
- Customization Support
- Sync header bypass mode for CXL supported to reduce latency.
- Drift buffer support* to reduce latency
Deliverables
- Verilog soft IP
- Sample testbench
Technical Specifications
Availability
Immediate
Related IPs
- Compute Express Link (CXL) 2.0 Controller
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- CXL 2.0 Dual Mode Controller
- CXL 2.0 Integrity and Data Encryption Security Module
- CXL 3.0 Retimer
- Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications