The Common Public Radio Interface (CPRI) Altera® FPGA IP core implements the CPRI Specification V7.0. CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE). The IP core targets high-performance, remote radio network applications. You can configure the CPRI Altera® FPGA IP core as an RE or an REC.
CPRI Altera® FPGA IP
Overview
Key Features
- Compliant with the Common Public Radio Interface (CPRI) Specification v7.0 (2015-10-09) Interface Specification.
- Supports radio equipment controller (REC) and radio equipment (RE) module configurations.
- Configurable CPRI line bit rate auto-rate negotiation support using Altera® FPGA on-chip high-speed transceivers.
- Configurable and runtime programmable synchronization mode: host port or agent port on a CPRI link.
- Transmitter (Tx) and receiver (Rx) deterministic latency and delay measurement and calibration. Note: Compliant with the CPRI Specification requirements R-19, R-20, R-20A, R-21, and R-21A.
- Configurable CPRI communication line bit rate (to 0.6144, 1.2288, 2.4576, 3.0720, 4.9152, 6.144, 8.11008, 9.8304, 10.1376, 12.16512 or 24.33024 Gbps) using Altera® FPGA on-chip high-speed transceivers.
Block Diagram
