Controllers for CCIX 25G supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications targeting automotive

Overview

Key Features

• Supports all required features of the CCIX 1.1 specification, including 32GT/s, and ESM support for 25GT/s and 20GT/s
• Supports all required features of the PCI Express 5.0, 4.0, 3.1, 2.1 and 1.1 specifications
• Supports up to sixteen 32.0 25.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
• Available in 128-, 256- or 512-bit datapath widths for maximum flexibility
• Supports PHYs with 8-, 16-, or 32-bit interfaces including variable clock and variable data modes
• Full transaction layer, data link layer and physical layer
• Application interfaces include the time-proven Synopsys native interface with extensions for CCIX, or the optional ARM® AMBA® 4 AXI, or AMBA 3 AXI application interface with extensions for CCIX
• Includes CCIX Transport DVSEC configuration space
• Optional embedded DMA controller with up to 8 read and 8 write channels for high throughput with minimal SoC resource overhead
• Configurable and efficient retry buffer design for low latency and area
• Supports automatic lane reversal and polarity inversion
• Supports the full range of maximum packet sizes (128B to 4KB) and read request sizes (128B to 4KB)
• Performs flow-control credit management, configurable for infinite credits for any traffic type
• Supports legacy INTx, MSI, and MSI-X interrupt semantics
• Configurable filtering rules for posted, non-posted and completion traffic
• Configurable BAR (up to 6) filtering, IO filtering, configuration filtering and completion lookup/timeout
• Support for multiple application clients
• In-band and out-of-band access to configuration space registers and external user application registers with local bus controller
• Expansion ROM, VPD, and Device Serial Number support
• Supports optional ECNs

Benefits

• Solution consists of digital controller, PHY and verification IP
• Supports all required features of the CCIX
• specification, including 32GT/s, and ESM support for 25GT/s and 20GT/s with targeted process ports at 16-nm and smaller
• Supports all required features of the PCIe
• 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s),
• 2.1 (5 GT/s) and 1.1 (2.5 GT/s), and 8-, 16-, or 32-bit PIPE specifications
• Controller provides reliability, availability, and serviceability (RAS) features, in addition to debug capabilities, error injection and statistics monitoring
• Low-power, compact PHY optimizes performance across voltage and temperature variations, and delivers superior signal integrity and jitter performance
• Verification IP offers configurable environments, complete port level checks and system-wide coherency checks

Applications

• Enterprise computing, storage area networks, SSD, switches, networking, routers, processors
• Computational accelerators, artificial intelligence, deep learning
• Graphics devices
• Desktops, laptops, workstations, and servers

Deliverables

• The coreConsultant utility to guide designers through the installation configuration, architectural exploration, verification, and implementation of the IP
• Verilog RTL code
• Example PHY interfaces
• ASIC and FPGA synthesis scripts
• Verification environment
• Synopsys Verification IP for the PCI Express
• Documentation: release notes, installation/integration guide, application notes, user manual

Technical Specifications