AndesCore™ AX25 is a compact 64-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is tailored for high-performance embedded applications that needs to access address space over 4GB. AX25 also supports the RISC-V P-extension (draft) DSP/SIMD ISA contributed by Andes, single- and double-precision floating point instructions, and MMU for Linux based applications. AX25 comes with options, including branch prediction for efficient branch execution, Instruction and Data caches, Local Memories for low-latency accesses, ECC for L1 memory soft error protection, and Andes Custom Extension™ (ACE) to add proprietary instructions to accelerate performance/power consumption critical spots.
AX25's 5-stage pipeline is optimized for high operating frequency and high performance. Features also includes PLIC and vectored interrupts for serving various types of system events, AXI or AHB 64-bit data bus for addressing up to 64-bit address, PowerBrake, QuickNap™ and WFI mode for low power and power management, and JTAG debug interface for development support.
Compact High-Speed 64-bit CPU for Real-time and Linux Applications
Overview
Key Features
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- DSP/SIMD ISA to boost the performance of digital signal processing
- Floating point extension
- Andes extensions, architected for performance and functionality enhancements
- Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
- 64-bit CPU architecture, enabling software to utilize the memory spaces far beyond 4G bytes imposed by 32-bit CPUs
- 16/32-bit mixable instruction format for compacting code density
- Branch predication to speed up control code
- Return Address Stack (RAS) to speed up procedure returns
- Memory Management Unit (MMU) and Physical Memory Protection (PMP)
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to reduce program code size
Benefits
- Performance
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extension
- Andes extensions, architected for performance and functionality enhancements
- Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
- 64-bit CPU architecture, enabling software to utilize the memory spaces far beyond 4G bytes imposed by 32-bit CPUs
- 16/32-bit mixable instruction format for compacting code density
- Branch predication to speed up control code
- Return Address Stack (RAS) to speed up procedure returns
- Memory Management Unit (MMU) and Physical Memory Protection (PMP)
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to reduce program code size
- Flexibility
- Easy arrangement of preemptive interrupts
- StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
- ECC or Parity check on level-one memories for fault protection
- Several configurations to tradeoff between core size and performance requirements
- Power Management
- PowerBrake, QuickNap™ and WFI (Wait For Interrupt) for power management at different occasions
Block Diagram
Applications
- Video processing
- Smart wireless switch/router
- Computer Vision and Pattern Recognition
- Machine/Deep Learning acceleration
Deliverables
- AX25 with AE350 Platform
- Pre-integrated AX25, PLIC, Debug Module, plus AXI/AHB Platform
Technical Specifications
Related IPs
- Compact High-Speed 32-bit CPU for Real-time and Linux Applications
- High-performance Processor for Real-time and Linux Applications
- Compact High-Speed 64-bit CPU Core
- Compact High-Speed 32-bit CPU Core with MemBoost and PMA
- Compact High-Speed 32-bit CPU Core
- Compact High-Speed 32-bit CPU Core with DSP