The eSi-CHACHA20-POLY1305 core is an easy to use APB hardware accelerator peripheral that is fully compliant with the IETF RFC7539 standard
Poly1305, along with the CHACHA20 encryption algorithm, has been specified for use in the TLS protocol, within RFC7905.
Combined ChaCha20 and Poly1305 core
Overview
Key Features
- Multiple processing modes:
- Poly1305 key generation based on ChaCha20
- ChaCha20 stream cipher
- Poly1305 authentication
- Additional Authentication Data (AAD)
- Composite Chacha20-Poly1305 processing for Authenticated Encryption with Associated Data (AEAD)
- Chacha20 processing of 64-bytes in as low as 13 clock cycles
- Poly1305 processing of 16-bytes in as low as 4 clock cycles
- Different processing architectures offering different balances between throughput/area
- AMBA 3 AHB slave interface for configuration and burst data transfers to perform processing
- Verilog 2001
Benefits
- Easy integration into Arm or other microprocessor SoC
- Small size and high performance
Applications
- Transport Layer Security (TLS)
- OpenSSH
- IPsec
- Ultra-low power embedded web-serverss
Deliverables
- RTL
- Testbench
- Software libraries
Technical Specifications
Foundry, Node
Any
Availability
Now
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