The CML buffer macro is a CML differential buffer for on-chip applications, and addresses a large portfolio of applications requiring CML signal levels on-chip. The buffer is designed for digital logic processes and uses robust design techniques to work in noisy SoC environments, ranging from high speed communication to low power consumer applications.
The buffer macro is implemented in Analog Bits’ proprietary architecture that uses core devices at core voltage only.
Buffer Operational Range Description Symbol Min Typ Max Units Input Frequency FCLK 1 600 MHz Input Duty Cycle tDI 40 60 % Total Area of Macro (45.120um [X] by 26.208um [Y]) A 0.0012 sq.mm Total Power (from supply) P 2.5 mW Output Load CL 500 fF Operational Voltage (Analog) VDDA 0.675 0.75 0.825 V Operational Temperature TOP -40 25 125 C