Capped LDO Regulator

Overview

HCLTech offers A low drop-out (LDO) voltage regulator has been designed in a 40nm tsmc technology. It offers benefits of low dropout voltage, micropower operation and miniaturized packaging.
The core of LDO voltage regulator consists of error amplifier, pass transistor and an external capacitor (Cout=1µf) with ESR=250m?, ESL=1.5nH which is used for regulator stability. Bandgap reference provides reference voltage (Vref) and is connected to the non-inverting terminal of error amplifier. The output of error amplifier drives gate of the pass transistor. The current flowing through the pass transistor is dependent on its dimensions. This dimension influences the drop-out voltage of the proposed LDO
Capped LDO regulator(hcl_ldo_1p0_30m_t40_v1) is designed for the input voltage of 1.8V and 30mA output current. The area of the regulator is 0.035 sq.mm. The quiescent current is 25µA and is stable over the entire range of output load current (0 mA to 30 mA).

Key Features

Output current range is 0-30mA
Short Circuit Current Limiting and Overtemperature Protection
Built–in Soft Start Circuit to Suppress Inrush Current
Current limit is 158mA.
Shutdown current< 900nA.
DC load regulation< 0.68%
DC line regulation < 0.041%
Transient overshoot and undershoot is within ±1%.
Area = 0.035sq.mm.

Block Diagram

Applications

Supply input for RC Oscillator
Supply input for Digital block like GP ADC and RF ADC

Technical Specifications

Foundry, Node

40 nm TSMC

Availability

Immediate

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