Camera Link Frame Grabber Channel Link Data Processor

Overview

Key Features

• Inclusive of all Camera Link defined camera configurations including the proposed 80 bit extensions which utilize one to three Channel Link or equivalent devices.
• Supports single camera or two independent base cameras for multi-view or 3D stereo applications.
• Fully synchronous pipeline architecture supports high speed implementation in low cost logic devices.
• Dynamic reconfiguration of the processing chain via register interface in addition to a user selected default setup.
• Data resynchronization of the three Channel Link interface inputs for coherent pixel data presentation at the output.
• Output image data presented on an eight byte memory mapped pixel interface as depicted in the Camera Link specification.
• Camera image enables are carried through to the output with an added data valid qualifier for the streaming synchronous output.
• Input link status and link data resynchronization status outputs available for increased visibility and enhanced debug capabilities.

Block Diagram

Deliverables

• The core is delivered as encrypted RTL and includes:
• Testbench and Verification Environment
• User Guide Documentation

Technical Specifications