Band Gap Reference
Overview
The designated IP is a very low power, high precision band gap reference circuit intended for integration into 130nm CMOS technology System on Chips. The low power bandgap limits the current consumption to 15μA and reference voltage variation to less than 3% over a temperature range of -40 to 125 deg C and over a wide range of voltage supply.
Key Features
- Fully integrated, compact design
- +/- 3% Accuracy.
- 3.3V± 10% power supply
- Low current consumption (15µA).
- No need of external capacitors.
- CMOS 130nm 1P8M,3.3V IO MOS
Benefits
- Very low current consumption (15 μA).
- Fast time to market
Deliverables
- GDSII & CDL Netlist
- .lef for PnR
- Datasheet
- Technical Reference Manual, Design Document
Technical Specifications
Foundry, Node
0.13u Tower
Maturity
Silicon Implemented
Availability
Immediate
TSMC
Pre-Silicon:
130nm
LP
Tower
Pre-Silicon:
130nm
Silicon Proven: 130nm
Silicon Proven: 130nm
Related IPs
- Band Gap IP, Input: 2.0V - 3.3V, VBG=1.23V, UMC 0.25um Logic process
- Band Gap IP, Input: 1.0V - 1.5V, VBG=0.615V, UMC 0.15um SP process
- Band Gap IP, Input: 1.0V - 1.2V, VBG=0.8V, UMC 0.13um LL/FSG process
- Band Gap IP, Input: 1.2V - 3.3V, VBG=0.615V, UMC 0.18um G2 process
- Band Gap IP, Input: 1.0V - 1.8V, VBG=0.615V, UMC 0.18um LL process
- Band Gap IP, Input: 1.2V - 4V, VBG=0.615V, UMC 0.18um LL process