AXI4-Stream to/from AXI Memory Map - AXI4-Stream Conversion to AXI Memory Map, 16 Channels

Overview

The DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Memory Map address, and signals a DMA Controller to read the data by way of a AXI4 Slave Memory Map read channel.

The DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE IP Core works with the DMA Controller (i.e. the DB-DMAC-MC-AXI Verilog RTL IP Core) to transfer data from an AXI4-Stream peripheral or AXI4-Stream Network Interface to either memory or another peripheral.

The companion IP, the DB-AXI4-MM-TO-STREAM-BRIDGE, works with the vendor DMA Controller to transfers data from memory or a peripheral to an AXI4-Stream peripheral or AXI4-Stream Network Interface.

Key Features

Converts AXI4-Stream Interface to AXI4/AXI3 Memory Map Data & Control Interface
- Standard release supports 16 AXI4-Stream Channels.
- More or less Channels optional. Contact Digital Blocks with requirements.
Works with Digital Blocks DMA Controller to support following data transfers:
- Peripheral-to-Memory
- Peripheral-to-Peripheral
- Network-to-Memory
- Network-to-Peripheral
Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024.
Interrupt Controller – for Diagnostics
Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.

Block Diagram

Deliverables

The DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE is available in synthesizable RTL Verilog or a technology-specific netlist for FPGAs, along with Synopsys Design Constraints, a simulation test bench with expected results, datasheet, and user manual.

Technical Specifications

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