AXI External Memory Controller
Overview
The AXI External Bus Interface (EBI) allows the processor to transmit and receive data to an external device, usually a memory (SRAM, Flash, etc.). The number of read wait states, the number of write wait states, and the memory width are all configurable through the APB register interface of the EBI. The EBI allows word, half-word, and byte width addressing to 64-bit, 32-bit, 16-bit, and 8-bit external devices.
Key Features
- Interfaces AXI bus to external SRAM or Parallel Flash devices
- AMBA® AXI Compatible
- Supports 8-bit, 16-bit, 32-bit and 64-bit external modes
- Supports byte (8-bit), halfword (16-bit), word (32-bit) and dword (64-bit) internal accesses
- Independent programmable wait states per device interface
- Selects up to 4 external devices
Block Diagram
Deliverables
- Verilog Source
- Complete Test Environment
- AXI Bus Functional Model
- C-Sample Code
Technical Specifications
Maturity
Silicon Proven
Availability
Now
Related IPs
- Quad SPI Flash Memory Controller
- Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
- Universal Multi-port Memory Controller for RLDRAM2/3, DDR4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
- Hyperbus Flash Memory Controller
- HBM2/2E Memory Controller Core
- AXI Quad SPI Controller with Execute in Place (XIP)