AXI USB 2.0 Device Controller
Overview
The Xilinx Universal Serial Bus 2.0 High Speed Device with Advance Micro controller Bus Architecture Advanced eXtensible Interface (AXI) enables USB connectivity to the user’s design with a minimal amount of resources. This interface is suitable for USB-centric, high-performance designs, bridges, and legacy port replacement operations.
Key Features
- AXI-4 based host Interface. AXI-4 Lite for Slave Interface and optional AXI-4 Master interface for DMA mode
- Supports High Speed and Full Speed USB 2.0 specification
- Supports high speed, high bandwidth isochronous transactions
- Supports up to eight endpoints, including one control endpoint 0. Endpoints 1 to 7 can be bulk, interrupt, or isochronous and are individually configurable
- Supports ULPI (Universal Transceiver Macrocell Interface (UTMI) + Low Pin Interface) to an external USB PHY
- Optional parameterized High-Speed Inter-Chip (HSIC) PHY support
- Access to ULPI PHY registers and parameterized ULPI PHY reset
- Optional feature support for unaligned transfers on the master interface
- Optional USB error detection, updates error count, and generates error interrupt
Technical Specifications
Related IPs
- USB 2.0 Device IP Core
- CXL 2.0 Controller with AXI
- USB 2.0 Device Controller version 4 with Active Clock Gating to save active power
- USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)
- USB 2.0 On-The-Go IP Core, Compliance Certified
- USB 3.0 Device IP Core