audio clock Generation, output nine kinds of 256*fs from 12M reference input
Overview
This PLL is designed for audio clock generation. The reference clock is 12MHz crystal or input clock. It supports 256*fs clock output, here fs is audio system sample rate of 32kHz/44.1kHz/48kHz. It integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other support circuits.
Key Features
- Process: GSMC 0.18um 1P4M mixed-signal process with MIM capacitor
- Supply Voltage: 3.3v +/-10%; 1.8v+/-10%
- Reference Input: 12MHz crystal or external clock
- Clock Output: 12.286MHz, 11.294MHz, 8.190MHz,6.143MHz, 5.647MHz, 4.095MHz, 3.071MHz, 2.823MHz, 2.048MHz
- Output Duty Cycle: 49~51% Current: <1.5mA
- Operating Temperature: 0~85c
- More details, please go to below website to contact VeriSilicon location sales:http://www.verisilicon.com/en/contactus.asp
Technical Specifications
Short description
audio clock Generation, output nine kinds of 256*fs from 12M reference input
Vendor
Vendor Name
Foundry, Node
audio clock Generation, output nine kinds of 256*fs from 12M reference input
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- The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process.